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september 17 , 201 2 | final | v1.1 1 1 ir3537 chl8510 12v high performance gate driver features ? drives both high - side and low - side mosfets in a synchronous buck configuration ? large drivers designed to drive 6nf server class fets o low - side driver C 4a source / 6a sink o high - side driver C 3a source / 4a sink o transition times & propagation delays < 20ns ? independent variable gate drive voltage for both high - and low - side drivers from 4.5v to 13.2v o improves efficiency o c ompatible with ir controller vgd feature ? integrated b ootstrap diode o reduces external component count ? capable of high switching frequencies from 200khz up to 1mhz ? configurable pwm modes of operation o ir active tri - level (atl), disables both mosfets in 30ns with no hold - off time o g eneric t ri - s tate pwm with hold - off ? adaptive non - overlap protection minimizes diode conduction time ? input supply under voltage protection ? thermally enhanced 10 - pin dfn package ? lead free rohs compliant package, msl level 1 applications ? multiphase synchronous buck converter for s erver a nd desktop computers using intel? and amd? vr solutions ? high efficiency and compact vrm ? high current dc/dc converters basic application figure 1: basic applications circuit description the ir3537/chl8510 is a high efficiency gate driver which can switch both high - side and low - side n - channel external mosfets in a synchronous buck converter. it is intended for use with international rectifiers digital pwm c ontroller s to provide a total voltage regulator (vr ) solution for todays advanced computing applications . the ir3537/chl8510 low - side driver is capable of rapidly switching large mosfets with low r ds ( on ) and large input capacitance used in high efficiency designs. the ir3537/chl8510 features individual control of both the high - and low - side gate drive voltages from 4.5v to 13.2v. this enables the optimization of switching and conduction loss es in the external mosfets. when used with ir s proprietary variable gate drive (vgd) technol ogy, a significant improvement in efficiency is observed across the entire load range. the ir3537/chl8510 can be configured to drive both the high - and low - side switches from the unique ir fast active tri - level (atl) pwm signal or a generic tri - state pwm m ode . the ir atl mode allows the controller to disable the high - and low - side fets in less than 30ns without the need for a dedicated disable pin. this improves vr transient performance, especially during load release. the integrated bootstrap diode reduce s external component count. the ir3537/chl8510 also f eatures an adaptive non - overlap control for shoot - through protection . this prevents cross conduction of both high - side and low - side mosfets and minimizes body diode conduction time to provide the best i n class efficiency . pin diagram figure 2 : ir3537/chl8510 package top view s w i t c h v c c p w m b o o t i r 3 5 3 7 / c h l 8 5 1 0 h i _ g a t e l o _ g a t e g n d c b o o t v c c p w m f r o m c o n t r o l l e r h s m o s f e t l s m o s f e t c v c c h v c c l v c c m o d e f l o a t f o r c h i l a t l m o d e r b o o t v v g d v c c s w i t c h r v c c g n d p i n 1 1 t o p v i e w 3 x 3 d f n 6 7 8 9 1 0 5 4 3 2 1 s w i t c h l v c c m o d e l o _ g a t e h i _ g a t e b o o t h v c c p w m g n d v c c
september 17 , 201 2 | final | v1.1 1 2 ir3537 chl8510 12v high performance gate driver ordering information ir3537 m ? ? ? ? ? chl85 1 0 ? ? ? package tape & reel qty part number d fn 3000 ir3537 mtrpbf dfn 750 ir3537 mtr 1 pbf package tape & reel qty part number d fn 3000 chl8510crt pbf C lead free tr C tape and reel package type (dfn) t C tape and reel r C package type (dfn) c C operating temperature (commercial standard)
september 17 , 201 2 | final | v1.1 1 3 ir3537 chl8510 12v high performance gate driver functional block dia gram figure 3 : ir3537/chl8510 functional block diagram pin descriptions pin # pin name pin description 1 boot floating bootstrap supply pin for the upper gate drive. connect a bootstrap capacitor between this pin and the switch pin. the bootstrap capacitor provides the charge to turn on the upper mosfet. see the internal bootstrap device section under description for guidance in choosing the capacitor value. 2 hvcc connect this pin to vcc (+12v) or to a separate supply between 4. 5v and 13.2v to provide a lower gate drive voltage on the high - sid e mosfet s . it is connected to the anode of the interna l bootstrap diode. place a high - quality low esr ceramic capacitor from this pin to gnd. 3 pwm the pwm signal is the control input for the driver from a 1.8v or 3.3v pwm signal . the pwm signal can enter three distinct states during operation; see the three - state pwm input section under description for further details. connect this pin to the pwm output of the controller. 4 vcc connect this pin to a +12v bias supply. place a high quality low esr ceramic capacitor from this pin to gnd. 5 lvcc connect this pin to v cc (+12v) or a separate supply voltage between 4.5v and 13.2v to vary the drive voltage on the low - side mosfet s. place a high - quality low esr ceramic capacitor from this pin to gnd. this pin must always be vcc + 0.7vdc. 6 lo_gate lower gate drive output. connect to gate of the low - side power n - channel mosfet. 7 gnd bias and reference ground. all signals are referenced to this node . it is also the power ground return of the driver. 8 mode this pin allows selection of the pwm signal voltage for 1.8v or 3.3v normal operation. floating this pin configures the driver for ir active tri - level (atl) using 1.8v pwm , and connecting this pin to ground configures the driver for generic active tri - stat e operation using 3.3v pwm. 9 switch connect this pin to the source of the upper mosfet and the drain of the lower mosfet. this pin provides a return path for the upper gate drive. 10 hi_gate upper gate drive output. connect to gate of high - side power n - channel mosfet. pad (11) gnd bias and reference ground. all signals are referenced to this node. it is also the power ground return of the driver. por , reference and control shoot through control lvcc lo_gate hi_gate gnd switch pwm vcc boot mode hvcc
september 17 , 201 2 | final | v1.1 1 4 ir3537 chl8510 12v high performance gate driver typical applications block diagrams figure 4 : 6 - phase v oltage regulator using ir3537/chl8510 mosfet drivers & chl8316 controller + 3 . 3 v v _ c p u 3 2 8 3 6 4 5 7 8 1 6 1 1 2 5 c h l 8 3 1 6 1 2 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 9 3 0 3 1 3 4 3 9 3 2 3 3 v i n s e n p w m 4 p w m 5 p w m 3 p w m 2 p w m 1 i s e n 5 v i d 5 v i d 6 v i d 1 v i d 3 v i d 4 v i d 2 v i d 0 v i d 7 i m o n v r _ r e a d y v c p u p s i # v c c r r e s e n v 1 8 a v r t n f r o m c p u i r t n 3 i s e n 4 2 1 4 7 i r t n 1 r c s p i r t n 2 r c s m i s e n 3 i s e n 2 i s e n 1 i r t n 4 + 1 2 v v v v v v v v v v f r o m s y s t e m l o a d v v r t n r _ i m o n c _ i m o n r c s c c s r s e r i e s r s e r i e s r t h r v i n _ 1 r v i n _ 2 4 5 4 6 4 3 4 4 4 1 4 2 i r t n 5 p w m 6 i s e n 6 i r t n 6 4 0 3 5 3 7 3 8 2 6 v r _ h o t t s e n r t h 2 6 s a d d r / g a m e r _ o f f 1 3 s a l e r t # + 3 . 3 v 1 4 1 5 s c l s d a s m b u s v v 1 0 g n d 2 9 n c 4 8 h v c c l o _ g a t e h i _ g a t e v c c g n d p w m l v c c 1 2 v v b o o t s w i t c h v v _ v g d c h l 8 5 1 0 1 2 v v v v _ v g d 1 2 v v v v _ v g d 1 2 v v v v _ v g d 1 2 v v v v _ v g d 1 2 v v v v _ v g d v 1 2 v v v _ v g d 2 7 v a r _ g a t e t o c p u t o c p u o p t i o n a l v a r i a b l e g a t e d r i v e c i r c u i t m o d e h v c c l o _ g a t e h i _ g a t e v c c g n d p w m l v c c b o o t s w i t c h m o d e h v c c l o _ g a t e h i _ g a t e v c c g n d p w m l v c c b o o t s w i t c h m o d e h v c c l o _ g a t e h i _ g a t e v c c g n d p w m l v c c b o o t s w i t c h m o d e h v c c l o _ g a t e h i _ g a t e v c c g n d p w m l v c c b o o t s w i t c h m o d e h v c c l o _ g a t e h i _ g a t e v c c g n d p w m l v c c b o o t s w i t c h m o d e h v c c l o _ g a t e h i _ g a t e v c c g n d p w m l v c c b o o t s w i t c h m o d e c h l 8 5 1 0 c h l 8 5 1 0 c h l 8 5 1 0 c h l 8 5 1 0 c h l 8 5 1 0 c h l 8 5 1 0
september 17 , 201 2 | final | v1.1 1 5 ir3537 chl8510 12v high performance gate driver absolute maximum rat ings boot +35.0v reference to gnd , +15v reference to switch pwm +7.0v vcc, hvcc +15.0v lvcc vcc+0.7vdc to a maximum of +15.0v lo_gate dc : - 0.3v to <0.3v above vcc , <200ns: - 2v to <0.3v above vcc gnd 0v+/ - 0v switch dc : - 0.3v to +15v, <20ns: 25v, <5ns: - 10v, <20 ns: - 4vdc and < 200 ns: - 2vdc hi_gate dc : switch C 0.3v to 0.3v above vboot , < 200ns: switch C 2v to 0.3v above vboot mode - 0.3v to +15.0v esd C charged device model jesd22 - c101 - c passes +/ - 1000v thermal information thermal resistance ( jc ) 3c/w thermal resistance ( ja ) 1 45 c/w maximum operating junction temperature 1 50 c maximum storage temperature range - 65c to 150c maximum lead temperature (soldering 10s) 300c note 1: ja is measured with the component mounted on a high effective thermal conductivity test board in free air. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sectio ns of the specifications are not implied.
september 17 , 201 2 | final | v1.1 1 6 ir3537 chl8510 12v high performance gate driver electrical specifications the electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. typical values represent the median values, which are related to 25c. recommended operatin g c onditions for reliab le operation with ma rgin recommended operating ambient temperature 0c to 85c recommended operating junction temperature 125c recommended supply voltage range +12 v 10% recommended lvcc & hvcc range (note lvcc must be vcc +0.7vdc) +4.5v to 13.2v e lectrical characteri stics parameter symbol conditions min typ max unit s upply supply bias current i vcc f pwm = 300khz, v vcc = 12v, no load - 7.0 - ma quiescent bias current i dd - 5.0 - ma vcc rising threshold for por - 8.6 - v vcc falling threshold for por - 7.1 - v pwm input active tri - level m ode (see figure 5) pwm input high threshold v ih(c_pwm) vcc = 12v - 1.0 - v pwm input low threshold v il(c_pwm) vcc = 12v - 0.8 - v pwm tri - l evel hi t hreshold v tl(c_pwm) vcc = 12v - 2.65 - v pwm tri - l evel low t hreshold v th(c_pwm) vcc = 12v - 2.55 - v pwm input current low i c_pwm v pwm = 0v - - 0.88 - ma pwm input current hi gh v pwm = 3.3v - - 10 - a pwm input tri - s tate mode (see figure 6 ) pwm input r ising threshold v ih(c_pwm) vcc = 12v - 1.65 - v pwm input f alling threshold v il(c_pwm) vcc = 12v - 1.3 - v tri - state lo_gate threshold - 0.85 - v tri - state lo_gate hysteresis - 200 - mv tri - state hi_gate threshold - 2.55 - v tri - state hi_gate hysteresis - 200 - mv tri - state hold - off t ime , note 1 - 80 - ns pwm input pull - up v oltage v pwm_pullup pwm input floating - 1.65 - v pwm input resistance r pwm pwm input floating - 3.75 - k
september 17 , 201 2 | final | v1.1 1 7 ir3537 chl8510 12v high performance gate driver high - s ide gate driver transition time, rising , note 1 t r(hs) 6nf load, v vcc = 12v, 10% - 90% - 21 - ns transition time, falling , note 1 t f(hs) 6nf load, v vcc = 12v, 10% - 90% - 18 - ns transition time, rising , note 1 t r(hs) 3nf load, v vcc = 12v, 10% - 90% - 15 - ns transition time , falling , note 1 t f(hs) 3nf load, v vcc = 12v, 10% - 90% - 12 - ns propagation delay , turn - on , note 1 t pdh(hs) 6nf load, v vcc = 12v, adaptive - 16 - ns propagation delay, turn - off , note 1 t pdl(ls) 6nf load, v vcc = 12v - 17 - ns propagation delay , exit tri - s tate , note 1 t pdts(hs_en) 6nf load, v vcc = 12v - 29 - ns propagation delay, enter tri - s tate , note 1 t pdts(hs_dis) 6nf load, v vcc = 12v - 16 - ns source current , note 1 i hs_source 6nf load, v vcc = 12v - 3.0 - a output impedance , s ourc ing r hs_source sink current at 1 00ma - 1.6 - ? sink curren t, note 1 i hs_sink 6nf load, v vcc = 12v - 4.0 - a output i mpedance , sinking r hs_sink sink current at 100ma - 0.6 - ? low - s ide gate driver transition time , rising , note 1 t f(ls) 6nf load, v vcc = 12v, 10% - 90% - 18 - ns transition time , falling , note 1 t r(ls) 6nf load, v vcc = 12v, 10% - 90% - 13 - ns transition time , ris ing , note 1 t f(ls) 3nf load, v vcc = 12v, 10% - 90% - 13 - ns transition time , fall ing , note 1 t r(ls) 3nf load, v vcc = 12v, 10% - 90% - 9 - ns propagation delay , turn - on , note 1 t pdh(ls) 6nf load, v vcc = 12v, adaptive - 17 - ns propagation delay , turn - off , note 1 t pdl(ls) 6nf load, v vcc = 12v - 13 - ns propagation delay , exit tri - s tate , note 1 t pdts(ls_en) 6nf load, v vcc = 12v - 26 - ns propagation delay , enter tri - s tate , note 1 t pdts(ls_dis) 6nf load, v vcc = 12v - 14 - ns source current , note 1 i ls_source 6nf load, v vcc = 12v - 4.0 - a output i mpedance , sourcing r ls_source sink current at 100ma - 1.5 - ? sink current , note 1 i ls_sink 6nf load, v vcc = 12v - 6 - a output impedance , sinking r ls_sink sink current at 100ma - 0.4 - ? note 1 : guaranteed by design but not tested in production.
september 17 , 201 2 | final | v1.1 1 8 ir3537 chl8510 12v high performance gate driver timing diagrams figure 5 : active tri - level m ode pwm, hi_gate and lo_gate s ignals figure 6 : tri - s tate m ode pwm, hi_gate and lo_gate s ignals
september 17 , 201 2 | final | v1.1 1 9 ir3537 chl8510 12v high performance gate driver general description the ir3537/chl8510 is a high efficiency, fast mosfet driver with large source and sink current capability. it can reli ably drive the external high - and low - side n - channel mosfets with large input capacitan ce at switching frequencies up to 1mhz. the proprietary ir active tri - level (atl) feature allows complete control over enable and disable of both mosfets using the pwm i nput signal from the controller. the driver is also compatible with a generic tri - state pwm signal. the active tri - level or tri - state is selectable by the mode pin. during normal operation the pwm transitions between low and high voltage levels to drive th e low - and high - side mosfets. the pwm signal falling edge transition to a low voltage threshold initiates the high - side driver turn off after a short propagation delay, t pdl(hs) . the dead time control circuit monitors the hi_gate and switch voltages to ens ure the high - side mosfet is turned off before the lo_gate voltage is allowed to rise to turn on the low - side mosfet. the pwm rising edge transition through the high - side turn - on threshold initiates the turn off of the low - side mosfet after a small propaga tion delay, t pdl(ls). the adaptive dead time circuit provides the appropriate dead time by determining if the falling lo_gate voltage threshold has been crossed before allowing the hi_gate voltage to rise and turn on the high - side mosfet , t pd h ( h s) . theory of operation power - on reset (por) the ir3537/chl8510 incorporates a power - on reset feature. this ensures that both the high - and low - side output drivers are made active only after the device supply voltage has exceeded a certain minimum operating t hreshold. the vcc supply is monitored and both the drivers are set to the low state, hold ing both external mosfets off. once vcc crosses the rising por threshold, the ir3537/chl8510 is reset and the outputs are held in the low state until a transition from tri - state to active operation is detected at the pwm input. during normal operation the drivers continue to remain active until the vcc falls below the falling por threshold. these por voltage threshold levels allow seam less functionality with interna ti o nal rectifiers digital controllers, such that the drivers are always active before the controller starts to provide the pwm signal and are inactive only after the controller shuts down. integrated bootstrap diode the ir3537/chl8510 features an integrated bootstrap diode to reduce external component count. this enables the ir3537/chl8510 to be used effectively in cost and space sensitive designs. the bootstrap circuit is used to establish the gate voltage for the high - side driver. it consists of a diode and capacitor connected between the switch and boot pins of the device. integrating the diode within the ir3537/ chl8510, results in the need for an external boot capacitor only. the bootstrap capacitor is charged through the diode and injects this charge into the high - side mosfet input capaci tance when pwm signal goes high. pwm mode selection the ir3537/chl8510 features a mode pin which allows operation with different pwm signal levels. the ir3537/chl8510 is capable of driving external mosfets based on o ne of two different tri - level pwm input signals from a controller. floating the mode pin enables the ir3537/chl8510 to switch external fets based on the ir active tri - level mode. in atl mode, the pwm voltage level is from 0v to 1.8v for low to high transitions. a pwm voltage level greater than the tri - state hi_gate threshold disables switching of both mosfets. grounding the mode pin enables the
september 17 , 201 2 | final | v1.1 1 10 ir3537 chl8510 12v high performance gate driver ir3537/chl8510 to switch fets based on a ge neric tri - state signaling with the pwm signal from 0v to 3.3v for low to high transitions. a pwm voltage level in the tri - state window between 1.23v and 1.82v for 80ns results in disabling both external mosfets. ir active tri - level pwm input sign al the ir3 537/chl8510 gate drivers are driven by a unique tri - level pwm control signal provided by the international rectifiers digital pwm controllers. during normal operation, the rising and falling edges of the pwm signal transitions between 0v and 1.8v to switc h the lo_gate and hi_gate. to force both driver outputs low simultaneously, the pwm signal crosses a tri - state voltage level higher than the tri - state hi_gate threshold. this threshold based tri - state results in a very fast disable with only a small tri - st ate propagation delay. mosfet switching resumes when the pwm signal falls below the tri - state threshold into the normal operating voltage range. this fast tri - state operation eliminates the need for the pwm signal to dwell in the shutdown window, eliminat ing any hold - off time. in addition, the disable delay time is not affected by the pwm trace routing capacitance. a dedicated enable pin is not required which simplifies the routing and layout in applications with a limited number of board layers. it als o provides switching free of shoot through for pwm transition times of up to 20ns. the ir3537/chl8510 is therefore tolerant of stray cap acitance on the pwm signal line s . the ir3537/chl8510 provides a 0.88ma typical pull - up current to drive the pwm input to the tri - state condition of 3.3v when the pwm controller output is in its high impedance state. the 0.88ma typical current is designed for driving worst case stray capacitances and transition the ir3537/chl8510 into the tri - state condition rapidly to avoid a prolonged period of conduction of the high - or low - side mosfets during faults. once the pwm signal has been pulled up, the current is disab led to reduce power consumption. diode emulation during load release one advantage of atl is the abil ity to quickl y turn - off all low - side mosfets during a load release event. this is known as diode emulation since all the load current is forced to flow momentarily through the body diodes of the mosfets. this results in a much lower overshoot on the output voltage as c an b e seen in figure 7 . figure 7 : output voltage overshoot reduction with body - brakin g start up during initial startup, the ir3537/chl8510 holds both high - and low - side drivers low even after por threshold is reached. this mode is maintained while the pwm signal is pulled to the tri - state threshold level greater than the tri - state hi_gate threshold and until it transitions ou t of tri - state. it is this initial transition out of the tri - state which enables both drivers to switch based on the normal pwm voltage levels. this startup also ensures that any undetermined pwm signal levels from a controller in pre - por state will not result in high or low - side mosfet turn on until t he controller is out of its por. note: the chl8510/ir3537 driver requires that the lvcc and vcc supply voltages be sequenced and operated under all start - up, operating, and shutdown conditions such that vcc is always greater than lv cc - 0.7vdc. failure to do this properly can cause catastrophic damage to the chl8510/ir3537 driver. high - side driver the high - side driver drives an external floating n - channel mosfet which can be switched at up to 1mhz. an exte rnal bootstrap circuit referenced to the switch node, consisting of a boot diode and capacitor is used to bias the external mosfet gate. when the switch node is at ground, the boot capacitor is charged to the voltage on the hvcc pin less the forward drop of the diode. this stored charge is used to turn on the high - side mosfet when the pwm signal goes high. once the high - side mosfet is turned on, the switch voltage is raised to the supply voltage , and the boot voltage is equal to the i_out 105a to 10a v_out without diode emulation overshoots ~25mv over 0a level i_out 105a to 10a v_out without diode emulation overshoots ~25mv over 0a level v_out with diode emulation overshoot within 0a level results in reduction of 30mv overshoot
september 17 , 201 2 | final | v1.1 1 11 ir3537 chl8510 12v high performance gate driver supply voltage plus the hvcc voltage less the diode forward voltage. when the pwm signal goes low, the mosfet is turned off by pulling the mo sfet gate to the switch voltage. low - side driver the ir3537/chl8510 low - side driver is designed to drive an external n - channel mosfet refe renced to ground at up to 1mhz. the low - side driver is connected interna lly to the lvcc supply voltage. adaptive dead time a djustment in a synchronous buck configuration, dead time between the turn off of one gate and turn on of the other is necessary to p revent simultaneous conducti on of the external mosfets preventing a shoot - through condition which would result in a short of the supply voltage to ground. a fixed dead time does not provide optimal performance across a variety of mosfets and board layouts. the ir3537/chl8510 provides an adaptive dead time adjustment. this feature minimizes dead time which maximizes efficiency. the break before make adaptive design is achieved by monitoring gate and switch voltages to determine off status of a mosfet. it also provides zero - voltage switching (zvs) of the low - side mosfet with minimum current conduction through its body - diode. when the pwm is switching between 1.8v and 0v, its falling edge transition from high to low will turn off the high - side gate driver. the adaptive dead time circuit monitors the hi_gate and the switch node voltages during the high - side mosfet turn off. when the hi_gate falls below 1 .7v above the switch node potential or the switch node voltage drops below 0.8v, the high - side mosfet is determined to be turned off , and the lo_gate turn - on is initiated . this turns on the external low - side mosfet. the rising edge transition of the pwm si gnal from low to high voltage causes the low - side gate driver to turn off. the adaptive circuit monitors the voltage at lo_gate and when it falls below 1.7v, the low - side mosfet is turned off , and the high - side mosfet turn - on is initiated . this turns on th e external high - side mosfet. independent variable gate voltage the ir3537/chl8510 features independent variable gate voltages for both the high - and low - side drivers . this enables implementation of the variable gate drive (vgd) feature in vr circuits using the ir multiphase controllers to improve efficiency . the voltage applied to the hvcc and lvcc pins of ir3537/chl8510 determines the gate voltage on the external mosf ets. these pins may be powered from independent voltage sources or tied together to a common voltage source. variation in the gate voltage allows efficiency to be optimized across the load current range by trading off conduction and switching losses. incre asing the voltage across a mosfet gate, results in reduced r dson which lowers the mosfet conduction losses, but also raises the gate charge which increases the switching losses. the voltage on each hvcc and lvcc pin, and thus the gate drive voltage of the chl8510, can be varied from 4.5v to 13.2v . the international rectifiers digital multiphase controllers provide a unique var_gate output which varies inversely with the vr output current. the var_gate output is designed to be used with an external circuit and provide the optimum voltage across the ir3537/chl8510 s hvcc and lvcc pins for optimum system e fficiency across the load range.
september 17 , 201 2 | final | v1.1 1 12 ir3537 chl8510 12v high performance gate driver application informat ion figure 1 shows the typical applications circuit for the ir3537/chl8510 . bootstrap circuit once t he high - side mosfet selection is made, the bootstrap circuit can be defined. the integrated boot diode of the ir3537/chl8510 reduces the external component count in cost and space sensitive designs. for ultra high efficiency designs, an external bootstrap diode is recommended. the bootstrap capacitor c boot stores the charge and provides the voltage required to drive the external high - side mosfet gate. the minimum capacitor value can be defined by: c boot = q hs_mosfet_gate / ?v boot where , ? q hs_mosfet_ gate is the total gate charge of the high - side external mosfet(s) ? ? v b oot is the droop allowed on the boot strap capacitor voltage ( at the high - side mosfet gate) if an external boot strap diode is used, d boot must be capable of handling the average and peak curre nts, i d_ avg and i d_ peak , and also the maximum supply voltage. i d_avg = q hs_mosfet_gate x f sw_max where , ? f sw_max is the controllers maximum switching frequency . the i d_ peak rating of the diode is determined by actual circuit measurements. the i d_peak rating of the diode is determined by actual circuit measurements . a series resistor (r boot ) of 1 to 4, is added to limit the surge current into the boot capacitor on start - up. this resistor can also be used to set the rising slew rate of the high - side mosfet gate drive (hi_gate) to help slow the rise time of the switch node for reduced ringing. supply decoupling ca pacitor decoupling to the ir3537/chl8510 is provided by a bypass capacitor c v cc located close to the supply input pin. a 1f, low esr, multi layer ceramic capacitor is recommended. a series resistor rvcc, typically 10, is added in series with the supply voltage to filter high frequency ringing and noise. pcb layout considera tions pcb layout and design is important to driver performance in v oltage regulator circuits due to the high current slew rate (di/dt) during mosfet switching. ? locate all power components in each phase as close to each other as practically possible in order to minimize parasitics and losses, allowing for reasonable airflo w . ? input supply decoupling and bootstrap capacitors should be physically close to their respective ic pins. ? high current paths like the gate driver traces should be as wide and short as practically possible. ? trace inductances to the high - and low - side mosf ets should be minimized. ? the ground connection of the ic should be as close as possible to the low - side mosfet source. ? use of a copper plane under and around the ic and thermal vias connected to buried copper layers improves the thermal p erformance.
september 17 , 201 2 | final | v1.1 1 13 ir3537 chl8510 12v high performance gate driver marking in formation figure 8: marking information for chl8510 figure 9: marking information for ir3537 8510 zzz - xx ayyww part # lot & wafer code assembler/date code pin 1 3537 ywlcx pin 1 part # date/lot/marking code a assembly site code
september 17 , 201 2 | final | v1.1 1 14 ir3537 chl8510 12v high performance gate driver package information figure 10 : dfn 3x3mm, 10 - pin
september 17 , 201 2 | final | v1.1 1 15 ir3537 chl8510 12v high performance gate driver data and specifications subject to change without notice. this product will be designed and qualified for the consumer market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information . www.irf.com

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